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Interrupts and Events Registers

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4.6.2.56 UDMACH3BSEL Register (Offset = 51Ch) [reset = X]

UDMACH3BSEL is shown in Figure 4-65 and described in Table 4-71.

Output Selection for DMA Channel 3 REQ

Figure 4-65. UDMACH3BSEL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-28h

Table 4-71. UDMACH3BSEL Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R 28h

Read only selection value

28h = SSI0 RX DMA burst request , controlled by

SSI0:DMACR.RXDMAE

340

Interrupts and Events SWCU117A–February 2015–Revised March 2015

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