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Coretex-M3 Core Registers

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2.5.1 Core Register Map

Table 2-2. Processor Register Map

Name Type Reset Description Link

R0 R/W – Cortex general-purpose register 0 See Section 2.5.2.1.

R1 R/W – Cortex general-purpose register 1 See Section 2.5.2.2.

R2 R/W – Cortex general-purpose register 2 See Section 2.5.2.3.

R3 R/W – Cortex general-purpose register 3 See Section 2.5.2.4.

R4 R/W – Cortex general-purpose register 4 See Section 2.5.2.5.

R5 R/W – Cortex general-purpose register 5 See Section 2.5.2.6.

R6 R/W – Cortex general-purpose register 6 See Section 2.5.2.7.

R7 R/W – Cortex general-purpose register 7 See Section 2.5.2.8.

R8 R/W – Cortex general-purpose register 8 See Section 2.5.2.9.

R9 R/W – Cortex general-purpose register 9 See Section 2.5.2.10.

R10 R/W – Cortex general-purpose register 10 See Section 2.5.2.11.

R11 R/W – Cortex general-purpose register 11 See Section 2.5.2.12.

R12 R/W – Cortex general-purpose register 12 See Section 2.5.2.13.

SP R/W – Stack pointer See Section 2.5.2.14.

LR R/W 0xFFFF FFFF Link register See Section 2.5.2.15.

PC R/W – Program counter See Section 2.5.2.16.

PSR R/W 0x0100 0000 Program status register See Section 2.5.2.17.

PRIMASK R/W 0x0000 0000 Priority mask register See Section 2.5.2.18.

FAULTMASK R/W 0x0000 0000 Fault mask register See Section 2.5.2.19.

BASEPRI R/W 0x0000 0000 Base priority mask register See Section 2.5.2.20.

CONTROL R/W 0x0000 0000 Control register See Section 2.5.2.21.

2.5.2 Core Register Descriptions

This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3. The core

registers are not memory mapped and are accessed by register name rather than offset.

NOTE: The register type shown in the register descriptions refers to type during program

execution in thread mode and handler mode. Debug access can differ.

2.5.2.1 Cortex General-Purpose Register 0 (R0)

Table 2-3. Cortex General-Purpose Register 0 (R0)

Address Offset Reset –

Physical Address Instance

Description The R0 registers are 32-bit general-purpose registers for data operations and can be accessed from

either privileged or unprivileged mode.

Type R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA

Bits Field Name Description Type Reset

31:0 DATA Register data RW —

The Cortex-M3 Processor SWCU117A–February 2015–Revised March 2015

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