User manual

www.ti.com

Interrupts and Events Registers

4.6.2.53 UDMACH2SSEL Register (Offset = 510h) [reset = X]

UDMACH2SSEL is shown in Figure 4-62 and described in Table 4-68.

Output Selection for DMA Channel 2 SREQ

Figure 4-62. UDMACH2SSEL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-33h

Table 4-68. UDMACH2SSEL Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R 33h

Read only selection value

33h = UART0 TX DMA single request, controlled by

UART0:DMACTL.TXDMAE

337

SWCU117A–February 2015–Revised March 2015 Interrupts and Events

Submit Documentation Feedback