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Interrupts and Events Registers

4.6.2.33 CPUIRQSEL32 Register (Offset = 80h) [reset = X]

CPUIRQSEL32 is shown in Figure 4-42 and described in Table 4-48.

Output Selection for CPU Interrupt 32

Figure 4-42. CPUIRQSEL32 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-73h

Table 4-48. CPUIRQSEL32 Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R 73h

Read only selection value

73h = AUX ADC interrupt event, corresponds to

AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags are found

here [AUX_EVCTL:EVTOMCUFLAGS.ADC*]

305

SWCU117A–February 2015–Revised March 2015 Interrupts and Events

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