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Interrupts and Events Registers

4.6.2.29 CPUIRQSEL28 Register (Offset = 70h) [reset = X]

CPUIRQSEL28 is shown in Figure 4-38 and described in Table 4-44.

Output Selection for CPU Interrupt 28

Figure 4-38. CPUIRQSEL28 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-Bh

Table 4-44. CPUIRQSEL28 Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R Bh

Read only selection value

Bh = AUX combined event, the corresponding flag register is here

AUX_EVCTL:EVTOMCUFLAGS

301

SWCU117A–February 2015–Revised March 2015 Interrupts and Events

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