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Interrupts and Events Registers

4.6.2.27 CPUIRQSEL26 Register (Offset = 68h) [reset = X]

CPUIRQSEL26 is shown in Figure 4-36 and described in Table 4-42.

Output Selection for CPU Interrupt 26

Figure 4-36. CPUIRQSEL26 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-15h

Table 4-42. CPUIRQSEL26 Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R 15h

Read only selection value

15h = FLASH controller error event, the status flags are

FLASH:FEDACSTAT.FSM_DONE and

FLASH:FEDACSTAT.RVF_INT

299

SWCU117A–February 2015–Revised March 2015 Interrupts and Events

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