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www.ti.com The Cortex-M3 Processor Introduction
2.1 The Cortex-M3 Processor Introduction
The ARM
®
Cortex™-M3 processor provides a high-performance, low-cost platform that meets the system
requirements of minimal memory implementation, reduced pin count, and low power consumption. The
following features included:
• 32-bit ARM Cortex-M3 architecture optimized for small-footprint, embedded applications
• Outstanding processing performance combined with fast interrupt handling
• Thumb
®
-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM
core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of
a few kilobytes of memory for microcontroller-class applications:
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
– Unaligned data access, enabling data to be efficiently packed into memory
• Fast code execution permits slower processor clock or increases sleep mode time
• Harvard architecture characterized by separate buses for instruction and data
• Efficient processor core, system and memories
• Hardware division and fast digital-signal-processing orientated multiply accumulate
• Saturating arithmetic for signal processing
• Deterministic, high-performance interrupt handling for time-critical applications
• Enhanced system debug with extensive breakpoint and trace capabilities
• Full debug with data matching for watch point generation.
– DWT
– JTAG Debut port
– FPB
• Migration from the ARM7™ processor family for better performance and power efficiency
• Standard trace support
– ITM
– TPIU with asynchronous Serial Wire Output (SWO)
• Optimized for single-cycle flash memory use
• Ultra-low power consumption with integrated sleep modes
• 48-MHz operation
2.2 Block Diagram
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard
architecture, making it ideal for demanding embedded applications. The processor delivers exceptional
power efficiency through an efficient instruction set and extensively optimized design, which provides high-
end processing hardware. The instruction set includes a range of single-cycle and SIMD multiplication and
multiply-with-accumulate capabilities, saturating arithmetic, and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled
system components that reduce processor area while significantly improving interrupt handling and
system-debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction set
based on Thumb-2 technology; thus ensuring high code density and reduced program memory
requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern
32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
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SWCU117A–February 2015–Revised March 2015 The Cortex-M3 Processor
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