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Interrupts and Events Registers

4.6.2.7 CPUIRQSEL6 Register (Offset = 18h) [reset = X]

CPUIRQSEL6 is shown in Figure 4-16 and described in Table 4-22.

Output Selection for CPU Interrupt 6

Figure 4-16. CPUIRQSEL6 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-1Ch

Table 4-22. CPUIRQSEL6 Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R 1Ch

Read only selection value

1Ch = AUX software event 0, triggered by

AUX_EVCTL:SWEVSET.SWEV0, also available as AUX_EVENT0

AON wake up event. MCU domain wakeup control

AON_EVENT:MCUWUSEL AUX domain wakeup control

AON_EVENT:AUXWUSEL

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SWCU117A–February 2015–Revised March 2015 Interrupts and Events

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