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Interrupts and Events Registers

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4.6.2.6 CPUIRQSEL5 Register (Offset = 14h) [reset = X]

CPUIRQSEL5 is shown in Figure 4-15 and described in Table 4-21.

Output Selection for CPU Interrupt 5

Figure 4-15. CPUIRQSEL5 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-24h

Table 4-21. CPUIRQSEL5 Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R 24h

Read only selection value

24h = UART0 combined interrupt, interrupt flags are found here

UART0:MIS

278

Interrupts and Events SWCU117A–February 2015–Revised March 2015

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