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Interrupts and Events Registers

4.6.2.1 CPUIRQSEL0 Register (Offset = 0h) [reset = X]

CPUIRQSEL0 is shown in Figure 4-10 and described in Table 4-16.

Output Selection for CPU Interrupt 0

Figure 4-10. CPUIRQSEL0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-4h

Table 4-16. CPUIRQSEL0 Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R 4h

Read only selection value

4h = Edge detect event from IOC. Configureded by the

IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings

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SWCU117A–February 2015–Revised March 2015 Interrupts and Events

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