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Interrupts and Events Registers
Table 4-15. EVENT Registers (continued)
Offset Acronym Register Name Section
200h GPT0ACAPTSEL Output Selection for GPT0 0 Section 4.6.2.45
204h GPT0BCAPTSEL Output Selection for GPT0 1 Section 4.6.2.46
300h GPT1ACAPTSEL Output Selection for GPT1 0 Section 4.6.2.47
304h GPT1BCAPTSEL Output Selection for GPT1 1 Section 4.6.2.48
400h GPT2ACAPTSEL Output Selection for GPT2 0 Section 4.6.2.49
404h GPT2BCAPTSEL Output Selection for GPT2 1 Section 4.6.2.50
508h UDMACH1SSEL Output Selection for DMA Channel 1 SREQ Section 4.6.2.51
50Ch UDMACH1BSEL Output Selection for DMA Channel 1 REQ Section 4.6.2.52
510h UDMACH2SSEL Output Selection for DMA Channel 2 SREQ Section 4.6.2.53
514h UDMACH2BSEL Output Selection for DMA Channel 2 REQ Section 4.6.2.54
518h UDMACH3SSEL Output Selection for DMA Channel 3 SREQ Section 4.6.2.55
51Ch UDMACH3BSEL Output Selection for DMA Channel 3 REQ Section 4.6.2.56
520h UDMACH4SSEL Output Selection for DMA Channel 4 SREQ Section 4.6.2.57
524h UDMACH4BSEL Output Selection for DMA Channel 4 REQ Section 4.6.2.58
528h UDMACH5SSEL Output Selection for DMA Channel 5 SREQ Section 4.6.2.59
52Ch UDMACH5BSEL Output Selection for DMA Channel 5 REQ Section 4.6.2.60
530h UDMACH6SSEL Output Selection for DMA Channel 6 SREQ Section 4.6.2.61
534h UDMACH6BSEL Output Selection for DMA Channel 6 REQ Section 4.6.2.62
538h UDMACH7SSEL Output Selection for DMA Channel 7 SREQ Section 4.6.2.63
53Ch UDMACH7BSEL Output Selection for DMA Channel 7 REQ Section 4.6.2.64
540h UDMACH8SSEL Output Selection for DMA Channel 8 SREQ Section 4.6.2.65
544h UDMACH8BSEL Output Selection for DMA Channel 8 REQ Section 4.6.2.66
548h UDMACH9SSEL Output Selection for DMA Channel 9 SREQ Section 4.6.2.67
54Ch UDMACH9BSEL Output Selection for DMA Channel 9 REQ Section 4.6.2.68
550h UDMACH10SSEL Output Selection for DMA Channel 10 SREQ Section 4.6.2.69
554h UDMACH10BSEL Output Selection for DMA Channel 10 REQ Section 4.6.2.70
558h UDMACH11SSEL Output Selection for DMA Channel 11 SREQ Section 4.6.2.71
55Ch UDMACH11BSEL Output Selection for DMA Channel 11 REQ Section 4.6.2.72
560h UDMACH12SSEL Output Selection for DMA Channel 12 SREQ Section 4.6.2.73
564h UDMACH12BSEL Output Selection for DMA Channel 12 REQ Section 4.6.2.74
56Ch UDMACH13BSEL Output Selection for DMA Channel 13 REQ Section 4.6.2.75
574h UDMACH14BSEL Output Selection for DMA Channel 14 REQ Section 4.6.2.76
57Ch UDMACH15BSEL Output Selection for DMA Channel 15 REQ Section 4.6.2.77
580h UDMACH16SSEL Output Selection for DMA Channel 16 SREQ Section 4.6.2.78
584h UDMACH16BSEL Output Selection for DMA Channel 16 REQ Section 4.6.2.79
588h UDMACH17SSEL Output Selection for DMA Channel 17 SREQ Section 4.6.2.80
58Ch UDMACH17BSEL Output Selection for DMA Channel 17 REQ Section 4.6.2.81
5A8h UDMACH21SSEL Output Selection for DMA Channel 21 SREQ Section 4.6.2.82
5ACh UDMACH21BSEL Output Selection for DMA Channel 21 REQ Section 4.6.2.83
5B0h UDMACH22SSEL Output Selection for DMA Channel 22 SREQ Section 4.6.2.84
5B4h UDMACH22BSEL Output Selection for DMA Channel 22 REQ Section 4.6.2.85
5B8h UDMACH23SSEL Output Selection for DMA Channel 23 SREQ Section 4.6.2.86
5BCh UDMACH23BSEL Output Selection for DMA Channel 23 REQ Section 4.6.2.87
5C0h UDMACH24SSEL Output Selection for DMA Channel 24 SREQ Section 4.6.2.88
5C4h UDMACH24BSEL Output Selection for DMA Channel 24 REQ Section 4.6.2.89
600h GPT3ACAPTSEL Output Selection for GPT3 0 Section 4.6.2.90
604h GPT3BCAPTSEL Output Selection for GPT3 1 Section 4.6.2.91
271
SWCU117A–February 2015–Revised March 2015 Interrupts and Events
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