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Table 4-8. MCU Event Fabric Input Events (continued)
Event No. Event Enum. Description
MCU domain wake-up control [AON_EVENT:MCUWUSEL.*]
AUX domain wake-up control [AON_EVENT:AUXWUSEL.*]
Combined interrupt for CPE-generated events. Corresponding flags are
0x1E RFC_CPE_1 here [RFC_DBELL:RFCPEIFG.*]. Only interrupts selected with CPE1 in
[RFC_DBELL:RFCPEIFG.*] can trigger a RFC_CPE_1 event.
0x1F NOT_USED
0x20 NOT_USED
0x21 NOT_USED
0x22 SSI0_COMB SSI0 combined interrupt, interrupt flags are found here [SSI0:MIS.*].
0x23 SSI1_COMB SSI0 combined interrupt, interrupt flags are found here [SSI1:MIS.*].
UART0 combined interrupt, interrupt flags are found here
0x24 UART0_COMB
[UART0:MIS.*].
0x25
0x26 DMA_ERR DMA bus error, corresponds to [UDMA0:ERROR.STATUS]
Combined DMA done corresponding flags are here
0x27 DMA_DONE_COMB
[UDMA0:REQDONE.*]
0x28 SSI0_RX_DMABREQ SSI0 RX DMA burst request, controlled by [SSI0:DMACR.RXDMAE]
0x29 SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by [SSI0:DMACR.RXDMAE]
0x2A SSI0_TX_DMABREQ SSI0 TX DMA burst request, controlled by [SSI0:DMACR.TXDMAE]
0x2B SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by [SSI0:DMACR.TXDMAE]
0x2C SSI1_RX_DMABREQ SSI1 RX DMA burst request, controlled by [SSI0:DMACR.RXDMAE]
0x2D SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by [SSI0:DMACR.RXDMAE]
0x2E SSI1_TX_DMABREQ SSI1 TX DMA burst request, controlled by [SSI0:DMACR.TXDMAE]
0x2F SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by [SSI0:DMACR.TXDMAE]
UART0 RX DMA burst request, controlled by
0x30 UART0_RX_DMABREQ
[UART0:DMACTL.RXDMAE]
UART0 RX DMA single request, controlled by
0x31 UART0_RX_DMASREQ
[UART0:DMACTL.RXDMAE]
UART0 TX DMA burst request, controlled by
0x32 UART0_TX_DMABREQ
[UART0:DMACTL.TXDMAE]
UART0 TX DMA single request, controlled by
0x33 UART0_TX_DMASREQ
[UART0:DMACTL.TXDMAE]
0x34
0x35
0x36
0x37
0x38 SPIS_COMB SPIS combined event, the flags are found here [SPIS:GPFLAGS.*]
SPIS RX FIFO DMA burst request, controlled by
0x39 SPIS_RXF_DMABREQ
[SPIS:CFG.TR_DMA_REQ_TYPE]
SPIS RX FIFO DMA single request, controlled by
0x3A SPIS_RXF_DMASREQ
[SPIS:CFG.TR_DMA_REQ_TYPE]
SPIS TX FIFO DMA burst request, controlled by
0x3B SPIS_TXF_DMABREQ
[SPIS:CFG.TX_DMA_REQ_TYPE]
SPIS TX FIFO DMA single request, controlled by
0x3C SPIS_TXF_DMASREQ
[SPIS:CFG.TX_DMA_REQ_TYPE]
0x3D GPT0A_CMP GPT0A compare event. Configured by [GPT0:TAMR.TCACT].
0x3E GPT0B_CMP GPT0B compare event. Configured by [GPT0:TBMR.TCACT].
0x3F GPT1A_CMP GPT1A compare event. Configured by [GPT1:TAMR.TCACT].
0x40 GPT1B_CMP GPT1B compare event. Configured by [GPT1:TBMR.TCACT].
0x41 GPT2A_CMP GPT2A compare event. Configured by [GPT2:TAMR.TCACT].
0x42 GPT2B_CMP GPT2B compare event. Configured by [GPT2:TBMR.TCACT].
242
Interrupts and Events SWCU117A–February 2015–Revised March 2015
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