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Table 4-4. Exception Return Behavior
EXC_RETURN[31:0] Description
0xFFFF FFF0 Reserved
Return to handler mode
0xFFFF FFF1 Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF FFF2 to 0xFFFF FFF8 Reserved
Return to thread mode
0xFFFF FFF9 Exception return uses state from MSP.
Execution uses MSP after return.
0xFFFF FFFA to 0xFFFF FFFC Reserved
Return to thread mode
0xFFFF FFFD Exception return uses state from PSP.
Execution uses PSP after return.
0xFFFF FFFE to 0xFFFF FFFF Reserved
4.2 Fault Handling
Faults are a subset of the exceptions (see Section 4.1, Exception Model). The following conditions
generate a fault:
• A bus error on an instruction fetch or vector table load or a data access
• An internally detected error such as an undefined instruction or an attempt to change state with a BX
instruction
4.2.1 Fault Types
Table 4-5 shows the types of fault, the handler used for the fault, the corresponding fault status register,
and the register bit that indicates the fault has occurred.
Table 4-5. Faults
Fault Handler Fault Status Register Bit Name
Bus error on a vector read Hard fault Hard Fault Status (HFSR) VECTTBL
Fault escalated to a hard fault Hard fault Hard Fault Status (HFSR) FORCED
Bus error during exception
Bus fault Bus Fault Status (BFSR) STKERR
stacking
Bus error during exception
Bus fault Bus Fault Status (BFSR) UNSTEKRR
unstacking
Bus error during instruction
Bus fault Bus Fault Status (BFSR) IBUSERR
prefetch
Precise data bus error Bus fault Bus Fault Status (BFSR) PRECISERR
Imprecise data bus error Bus fault Bus Fault Status (BFSR) IMPRECISERR
Attempt to access a
Usage fault Usage Fault Status (UFSR) NOCP
coprocessor
Undefined instruction Usage fault Usage Fault Status (UFSR) UNDEFINSTR
Attempt to enter an invalid
Usage fault Usage Fault Status (UFSR) INVSTATE
instruction set state
(1)
Invalid EXC_RETURN value Usage fault Usage Fault Status (UFSR) INVPC
Illegal unaligned load or store Usage fault Usage Fault Status (UFSR) UNALIGNED
Divide by 0 Usage fault Usage Fault Status (UFSR) DIVBYZERO
(1)
Trying to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI
continuation.
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SWCU117A–February 2015–Revised March 2015 Interrupts and Events
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