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Functional Overview

• Two transmission speeds:

– Standard (100 Kbps)

– Fast (400 Kbps)

• Clock low time-out interrupt

• Master and slave interrupt generation:

– Master generates interrupts when a TX or RX operation completes (or aborts due to an error)

– Slave generates interrupts when data is transferred or requested by a master or when a START or

STOP condition is detected

– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

1.3.8.3 I2S

An I2S module makes the CC26xx capable of communicating with external devices like CODECs,

DAC/ADCs, or DSPs. CC26xx will only support audio streaming formats like I2S, RJF, LJF, and DSP;

CC26xx will not support configuration of external devices. CC26xx will support both external and internally

generated bit clock and word clock (BCLK and WCLK).

1.3.8.4 SSI

An SSI module is a 4-wire bidirectional communications interface that converts data between parallel and

serial. The SSI performs serial-to-parallel conversion on data received from a peripheral device and

performs parallel-to-serial conversion on data transmitted to a peripheral device. The SSI can be

configured as either a master or slave device. As a slave device, the SSI can be configured to disable its

output, which allows coupling of a master device with multiple slave devices. The TX and RX paths are

buffered with separate internal FIFOs.

The SSI also includes a programmable bit rate clock divider and prescaler to generate the output serial

clock derived from the input clock of the SSI. Bit rates are generated based on the input clock, and the

maximum bit rate is determined by the connected peripheral.

The CC26xx includes two SSI modules with the following features:

• Programmable interface operation for Freescale SPI, MICROWIRE, or TI synchronous serial interfaces

• Master or slave operation

• Programmable clock bit rate and prescaler

• Separate TX and RX FIFOs, each 16 bits wide and eight locations deep

• Programmable data-frame size from 4 to 16 bits

• Internal loopback test mode for diagnostic and debug testing

• Standard FIFO-based interrupts and EoT interrupt

• Efficient transfers using the µDMA controller:

– Separate channels for TX and RX

– Receive single request asserted when data is in the FIFO; burst request is asserted when FIFO

contains four entries

– Transmit single request asserted when there is space in the FIFO; burst request is asserted when

FIFO contains four entries

SWCU117A–February 2015–Revised March 2015 Architectural Overview

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