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the dynamic range of the counter
• A simple counter used to measure time to completion and time used
• An internal clock source control based on missing and/or meeting durations. The COUNTFLAG bit in
the STCSR control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
The timer consists of three registers:
• SysTick Control and Status (STCSR): A control and status counter to configure its clock, enable the
counter, enable the SysTick interrupt, and determine counter status
• SysTick Reload Value (STRVR): The reload value for the counter, used to provide the wrap value of
the counter
• SysTick Current Value (STCVR): The current value of the counter
When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) to the
value in the STRRVR register on the next clock edge, then decrements on subsequent clocks. Clearing
the STRVR register disables the counter on the next wrap. When the counter reaches 0, the
COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
Writing to the STCVR register clears the register and the COUNTFLAG status bit. The write does not
trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the
register is accessed.
The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the
SysTick counter stops. Ensure that software uses aligned word accesses to access the SysTick registers.
NOTE: When the processor is halted for debugging, the counter does not decrement.
3.2.2 NVIC
This section describes the NVIC and the registers it uses. The NVIC supports:
• 34 interrupt lines
• A programmable priority level of 0 to 7 for each interrupt. A higher level corresponds to a lower priority,
so level 0 is the highest interrupt priority.
• Low-latency exception and interrupt handling
• Level and pulse detection of interrupt signals
• Dynamic reprioritization of interrupts
• Grouping of priority values into group priority and sub priority fields
• Interrupt tail-chaining
• An external nonmaskable interrupt (NMI)
The processor automatically stacks its state on exception entry and un-stacks this state on exception exit,
with no instruction overhead, providing low latency exception handling.
3.2.2.1 Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as
edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral de-asserts the
interrupt signal. The interrupt sources in CC26xx are normally level. That is, they stay active until the
interrupt source is cleared in the peripheral. Typically this happens because the interrupt service routine
(ISR) accesses the peripheral, causing it to clear the interrupt request. To ensure the NVIC detects the
interrupt, the peripheral must assert the interrupt signal for at least one clock cycle.
When the processor enters the ISR, it automatically removes the pending state from the interrupt (for
more information, see Hardware and Software Control of Interrupts). For a level-sensitive interrupt, if the
signal is not de-asserted before the processor returns from the ISR, the interrupt becomes pending again,
and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal
asserted until it no longer needs servicing.
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Cortex™-M3 Peripherals SWCU117A–February 2015–Revised March 2015
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