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Cortex-M3 Processor Registers

2.7.5.12 DEVID Register (Offset = FC8h) [reset = CA0h]

DEVID is shown in Figure 2-142 and described in Table 2-169.

Device ID

Figure 2-142. DEVID Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DEVID

R-CA0h

Table 2-169. DEVID Register Field Descriptions

Bit Field Type Reset Description

31-0 DEVID R CA0h

This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there

is no ETM present.

219

SWCU117A–February 2015–Revised March 2015

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