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Cortex-M3 Processor Registers

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2.7.5.5 FFSR Register (Offset = 300h) [reset = X]

FFSR is shown in Figure 2-135 and described in Table 2-162.

Formatter and Flush Status

Figure 2-135. FFSR Register

31 30 29 28 27 26 25 24

RESERVED

R-X

23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8

RESERVED

R-X

7 6 5 4 3 2 1 0

RESERVED FTNONSTOP RESERVED

R-X R-1h R-X

Table 2-162. FFSR Register Field Descriptions

Bit Field Type Reset Description

31-4 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

3 FTNONSTOP R 1h

0: Formatter can be stopped 1: Formatter cannot be stopped

2-0 RESERVED R X

This field always reads as zero

212

SWCU117A–February 2015–Revised March 2015

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