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Cortex-M3 Processor Registers

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2.7.5.3 ACPR Register (Offset = 10h) [reset = X]

ACPR is shown in Figure 2-133 and described in Table 2-160.

Async Clock Prescaler This register scales the baud rate of the asynchronous output.

Figure 2-133. ACPR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PRESCALER

R/W-X R/W-X

Table 2-160. ACPR Register Field Descriptions

Bit Field Type Reset Description

31-13 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

12-0 PRESCALER R/W X

Divisor for input trace clock is (PRESCALER + 1).

210

SWCU117A–February 2015–Revised March 2015

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