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Cortex-M3 Processor Registers
2.7.5.2 CSPSR Register (Offset = 4h) [reset = X]
CSPSR is shown in Figure 2-132 and described in Table 2-159.
Current Sync Port Size This register has the same format as SSPSR but only one bit can be set, and all
others must be zero. Writing values with more than one bit set, or setting a bit that is not indicated as
supported can cause Unpredictable behavior. On reset this defaults to the smallest possible port size, 1
bit.
Figure 2-132. CSPSR Register
31 30 29 28 27 26 25 24
RESERVED
R/W-X
23 22 21 20 19 18 17 16
RESERVED
R/W-X
15 14 13 12 11 10 9 8
RESERVED
R/W-X
7 6 5 4 3 2 1 0
RESERVED FOUR THREE TWO ONE
R/W-X R/W-X R/W-X R/W-X R/W-1h
Table 2-159. CSPSR Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
3 FOUR R/W X
4-bit port enable Writing values with more than one bit set in
CSPSR, or setting a bit that is not indicated as supported in SSPSR
can cause Unpredictable behavior.
2 THREE R/W X
3-bit port enable Writing values with more than one bit set in
CSPSR, or setting a bit that is not indicated as supported in SSPSR
can cause Unpredictable behavior.
1 TWO R/W X
2-bit port enable Writing values with more than one bit set in
CSPSR, or setting a bit that is not indicated as supported in SSPSR
can cause Unpredictable behavior.
0 ONE R/W 1h
1-bit port enable Writing values with more than one bit set in
CSPSR, or setting a bit that is not indicated as supported in SSPSR
can cause Unpredictable behavior.
209
SWCU117A–February 2015–Revised March 2015
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