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Cortex-M3 Processor Registers

2.7.5 CPU_TPIU Registers

Table 2-157 lists the memory-mapped registers for the CPU_TPIU. All register offset addresses not listed

in Table 2-157 should be considered as reserved locations and the register contents should not be

modified.

Table 2-157. CPU_TPIU Registers

Offset Acronym Register Name Section

0h SSPSR Supported Sync Port Sizes Section 2.7.5.1

4h CSPSR Current Sync Port Size Section 2.7.5.2

10h ACPR Async Clock Prescaler Section 2.7.5.3

F0h SPPR Selected Pin Protocol Section 2.7.5.4

300h FFSR Formatter and Flush Status Section 2.7.5.5

304h FFCR Formatter and Flush Control Section 2.7.5.6

308h FSCR Formatter Synchronization Counter Section 2.7.5.7

FA0h CLAIMMASK Claim Tag Mask Section 2.7.5.8

FA0h CLAIMSET Claim Tag Set Section 2.7.5.9

FA4h CLAIMTAG Current Claim Tag Section 2.7.5.10

FA4h CLAIMCLR Claim Tag Clear Section 2.7.5.11

FC8h DEVID Device ID Section 2.7.5.12

207

SWCU117A–February 2015–Revised March 2015

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