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Cortex-M3 Processor Registers www.ti.com
Table 2-155. DEMCR Register Field Descriptions (continued)
Bit Field Type Reset Description
16 MON_EN R/W X
Enable the debug monitor. When enabled, the System handler
priority register controls its priority level. If disabled, then all debug
events go to Hard fault. DHCSR.C_DEBUGEN overrides this bit.
Vector catching is semi-synchronous. When a matching event is
seen, a Halt is requested. Because the processor can only halt on
an instruction boundary, it must wait until the next instruction
boundary. As a result, it stops on the first instruction of the exception
handler. However, two special cases exist when a vector catch has
triggered: 1. If a fault is taken during vectoring, vector read or stack
push error, the halt occurs on the corresponding fault handler, for the
vector error or stack push. 2. If a late arriving interrupt comes in
during vectoring, it is not taken. That is, an implementation that
supports the late arrival optimization must suppress it in this case.
15-11 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
10 VC_HARDERR R/W X
Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is
cleared.
9 VC_INTERR R/W X
Debug trap on a fault occurring during an exception entry or return
sequence. Ignored when DHCSR.C_DEBUGEN is cleared.
8 VC_BUSERR R/W X
Debug Trap on normal Bus error. Ignored when
DHCSR.C_DEBUGEN is cleared.
7 VC_STATERR R/W X
Debug trap on Usage Fault state errors. Ignored when
DHCSR.C_DEBUGEN is cleared.
6 VC_CHKERR R/W X
Debug trap on Usage Fault enabled checking errors. Ignored when
DHCSR.C_DEBUGEN is cleared.
5 VC_NOCPERR R/W X
Debug trap on a UsageFault access to a Coprocessor. Ignored when
DHCSR.C_DEBUGEN is cleared.
4 VC_MMERR R/W X
Debug trap on Memory Management faults. Ignored when
DHCSR.C_DEBUGEN is cleared.
3-1 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
0 VC_CORERESET R/W X
Reset Vector Catch. Halt running system if Core reset occurs.
Ignored when DHCSR.C_DEBUGEN is cleared.
204
SWCU117A–February 2015–Revised March 2015
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