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www.ti.com Cortex-M3 Processor Registers
2.7.4.59 DEMCR Register (Offset = DFCh) [reset = X]
DEMCR is shown in Figure 2-129 and described in Table 2-155.
Debug Exception and Monitor Control The purpose of this register is vector catching and debug monitor
control. This register manages exception behavior under debug. Vector catching is only available to
halting debug. The upper halfword is for monitor controls and the lower halfword is for halting exception
support. This register is not reset on a system reset. This register is reset by a power-on reset. The fields
MON_EN, MON_PEND, MON_STEP and MON_REQ are always cleared on a core reset. The debug
monitor is enabled by software in the reset handler or later, or by the **AHB-AP** port. Vector catching is
semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only
halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the
first instruction of the exception handler. However, two special cases exist when a vector catch has
triggered: 1. If a fault is taken during a vector read or stack push error the halt occurs on the
corresponding fault handler for the vector error or stack push. 2. If a late arriving interrupt detected during
a vector read or stack push error it is not taken. That is, an implementation that supports the late arrival
optimization must suppress it in this case.
Figure 2-129. DEMCR Register
31 30 29 28 27 26 25 24
RESERVED TRCENA
R/W-X R/W-X
23 22 21 20 19 18 17 16
RESERVED MON_REQ MON_STEP MON_PEND MON_EN
R/W-X R/W-X R/W-X R/W-X R/W-X
15 14 13 12 11 10 9 8
RESERVED VC_HARDERR VC_INTERR VC_BUSERR
R/W-X R/W-X R/W-X R/W-X
7 6 5 4 3 2 1 0
VC_STATERR VC_CHKERR VC_NOCPERR VC_MMERR RESERVED VC_CORERES
ET
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
Table 2-155. DEMCR Register Field Descriptions
Bit Field Type Reset Description
31-25 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
24 TRCENA R/W X
This bit must be set to 1 to enable use of the trace and debug
blocks: DWT, ITM, ETM and TPIU. This enables control of power
usage unless tracing is required. The application can enable this, for
ITM use, or use by a debugger.
23-20 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
19 MON_REQ R/W X
This enables the monitor to identify how it wakes up. This bit clears
on a Core Reset. 0x0: Woken up by debug exception. 0x1: Woken
up by MON_PEND
18 MON_STEP R/W X
When MON_EN = 1, this steps the core. When MON_EN = 0, this bit
is ignored. This is the equivalent to DHCSR.C_STEP. Interrupts are
only stepped according to the priority of the monitor and settings of
PRIMASK, FAULTMASK, or BASEPRI.
17 MON_PEND R/W X
Pend the monitor to activate when priority permits. This can wake up
the monitor through the AHB-AP port. It is the equivalent to
DHCSR.C_HALT for Monitor debug. This register does not reset on
a system reset. It is only reset by a power-on reset. Software in the
reset handler or later, or by the DAP must enable the debug monitor.
203
SWCU117A–February 2015–Revised March 2015
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