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2.7.4.57 DCRSR Register (Offset = DF4h) [reset = 0h]
DCRSR is shown in Figure 2-127 and described in Table 2-153.
Deubg Core Register Selector The purpose of this register is to select the processor register to transfer
data to or from. This write-only register generates a handshake to the core to transfer data to or from
Debug Core Register Data Register and the selected register. Until this core transaction is complete,
DHCSR.S_REGRDY is 0. Note that writes to this register in any size but word are Unpredictable. Note
that PSR registers are fully accessible this way, whereas some read as 0 when using MRS instructions.
Note that all bits can be written, but some combinations cause a fault when execution is resumed.
Figure 2-127. DCRSR Register
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED REGWNR
W-0h W-0h
15 14 13 12 11 10 9 8
RESERVED
W-0h
7 6 5 4 3 2 1 0
RESERVED REGSEL
W-0h W-0h
Table 2-153. DCRSR Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED W 0h
Software should not rely on the value of a reserved. Write 0.
16 REGWNR W 0h
1: Write 0: Read
15-5 RESERVED W 0h
Software should not rely on the value of a reserved. Write 0.
4-0 REGSEL W 0h
Register select 0x00: R0 0x01: R1 0x02: R2 0x03: R3 0x04: R4
0x05: R5 0x06: R6 0x07: R7 0x08: R8 0x09: R9 0x0A: R10 0x0B:
R11 0x0C: R12 0x0D: Current SP 0x0E: LR 0x0F:
DebugReturnAddress 0x10: XPSR/flags, execution state information,
and exception number 0x11: MSP (Main SP) 0x12: PSP (Process
SP) 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 |
PRIMASK
201
SWCU117A–February 2015–Revised March 2015
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