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Cortex-M3 Processor Registers www.ti.com
Table 2-152. DHCSR Register Field Descriptions (continued)
Bit Field Type Reset Description
19 S_LOCKUP R/W X
Reads as one if the core is running (not halted) and a lockup
condition is present. When writing to this register, 1 must be written
this bit-field, otherwise the write operation is ignored and no bits are
written into the register.
18 S_SLEEP R/W X
Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-
EXIT**). Must use C_HALT to gain control or wait for interrupt to
wake-up. When writing to this register, 1 must be written this bit-field,
otherwise the write operation is ignored and no bits are written into
the register.
17 S_HALT R/W X
The core is in debug state when this bit is set. When writing to this
register, 1 must be written this bit-field, otherwise the write operation
is ignored and no bits are written into the register.
16 S_REGRDY R/W 0h
Register Read/Write on the Debug Core Register Selector register is
available. Last transfer is complete. When writing to this register, 1
must be written this bit-field, otherwise the write operation is ignored
and no bits are written into the register.
15-6 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
5 C_SNAPSTALL R/W X
If the core is stalled on a load/store operation the stall ceases and
the instruction is forced to complete. This enables Halting debug to
gain control of the core. It can only be set if: C_DEBUGEN = 1 and
C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates
that no instruction has advanced. This prevents misuse. The bus
state is Unpredictable when this is used. S_RETIRE_ST can detect
core stalls on load/store operations.
4 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
3 C_MASKINTS R/W X
Mask interrupts when stepping or running in halted debug. This
masking does not affect NMI, fault exceptions and SVC caused by
execution of the instructions. This bit must only be modified when
the processor is halted (S_HALT == 1). C_MASKINTS must be set
or cleared before halt is released (i.e., the writes to set or clear
C_MASKINTS and to set or clear C_HALT must be separate).
Modifying C_MASKINTS while the system is running with halting
debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause
unpredictable behavior.
2 C_STEP R/W X
Steps the core in halted debug. When C_DEBUGEN = 0, this bit has
no effect. Must only be modified when the processor is halted
(S_HALT == 1). Modifying C_STEP while the system is running with
halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may
cause unpredictable behavior.
1 C_HALT R/W X
Halts the core. This bit is set automatically when the core Halts. For
example Breakpoint. This bit clears on core reset.
0 C_DEBUGEN R/W X
Enables debug. This can only be written by AHB-AP and not by the
core. It is ignored when written by the core, which cannot set or clear
it. The core must write a 1 to it when writing C_HALT to halt itself.
The values of C_HALT, C_STEP and C_MASKINTS are ignored by
hardware when C_DEBUGEN = 0. The read values for C_HALT,
C_STEP and C_MASKINTS fields will be unknown to software when
C_DEBUGEN = 0.
200
SWCU117A–February 2015–Revised March 2015
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