User manual

Contents

Revision History.......................................................................................................................... 10

Preface....................................................................................................................................... 11

1 Architectural Overview........................................................................................................ 13

1.1 Target Applications......................................................................................................... 14

1.2 Overview..................................................................................................................... 14

1.3 Functional Overview ....................................................................................................... 17

1.3.1 ARM Cortex-M3 ................................................................................................... 17

1.3.2 On-Chip Memory .................................................................................................. 18

1.3.3 Radio................................................................................................................ 19

1.3.4 AES Engine With 128-Bit Key Support......................................................................... 19

1.3.5 General-Purpose Timers ......................................................................................... 20

1.3.6 Direct Memory Access............................................................................................ 20

1.3.7 System Control and Clock ....................................................................................... 21

1.3.8 Serial Communications Peripherals............................................................................. 21

1.3.9 Programmable IOs ................................................................................................ 24

1.3.10 Sensor Controller ................................................................................................ 24

1.3.11 Random Number Generator .................................................................................... 25

1.3.12 cJTAG and JTAG ................................................................................................ 25

1.3.13 Power Supply System ........................................................................................... 25

2 The Cortex-M3 Processor.................................................................................................... 28

2.1 The Cortex-M3 Processor Introduction.................................................................................. 29

2.2 Block Diagram .............................................................................................................. 29

2.3 Overview..................................................................................................................... 30

2.3.1 System-Level Interface ........................................................................................... 30

2.3.2 Integrated Configurable Debug.................................................................................. 30

2.3.3 Trace Port Interface Unit ......................................................................................... 31

2.3.4 Cortex-M3 System Component Details......................................................................... 31

2.4 Programming Model ....................................................................................................... 31

2.4.1 Processor Mode and Privilege Levels for Software Execution .............................................. 32

2.4.2 Stacks............................................................................................................... 32

2.4.3 Exceptions and Interrupts ........................................................................................ 32

2.4.4 Data Types......................................................................................................... 32

2.5 Coretex-M3 Core Registers............................................................................................... 33

2.5.1 Core Register Map ................................................................................................ 34

2.5.2 Core Register Descriptions ...................................................................................... 34

2.6 Instruction Set Summary .................................................................................................. 47

2.7 Cortex-M3 Processor Registers .......................................................................................... 50

2.7.1 CPU_ITM Registers............................................................................................... 51

2.7.2 CPU_DWT Registers ............................................................................................. 92

2.7.3 CPU_FPB Registers............................................................................................. 117

2.7.4 CPU_SCS Registers ............................................................................................ 129

2.7.5 CPU_TPIU Registers............................................................................................ 207

3 Cortex™-M3 Peripherals.................................................................................................... 220

3.1 Cortex™-M3 Peripherals Introduction.................................................................................. 221

Contents SWCU117A–February 2015–Revised March 2015

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