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Cortex-M3 Processor Registers

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2.7.4.55 CPACR Register (Offset = D88h) [reset = X]

CPACR is shown in Figure 2-125 and described in Table 2-151.

Coprocessor Access Control This register specifies the access privileges for coprocessors.

Figure 2-125. CPACR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

R/W-X

Table 2-151. CPACR Register Field Descriptions

Bit Field Type Reset Description

31-0 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

198

SWCU117A–February 2015–Revised March 2015

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