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Cortex-M3 Processor Registers

2.7.4.50 ID_ISAR0 Register (Offset = D60h) [reset = 1101110h]

ID_ISAR0 is shown in Figure 2-120 and described in Table 2-146.

ISA Feature 0 Information on the instruction set attributes register

Figure 2-120. ID_ISAR0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

R-1101110h

Table 2-146. ID_ISAR0 Register Field Descriptions

Bit Field Type Reset Description

31-0 RESERVED R 1101110h

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

193

SWCU117A–February 2015–Revised March 2015

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