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Cortex-M3 Processor Registers

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2.7.4.49 ID_MMFR3 Register (Offset = D5Ch) [reset = X]

ID_MMFR3 is shown in Figure 2-119 and described in Table 2-145.

Memory Model Feature 3 General information on the memory model and memory management support.

Figure 2-119. ID_MMFR3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

R-X

Table 2-145. ID_MMFR3 Register Field Descriptions

Bit Field Type Reset Description

31-0 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

192

SWCU117A–February 2015–Revised March 2015

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