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Cortex-M3 Processor Registers
2.7.4.48 ID_MMFR2 Register (Offset = D58h) [reset = X]
ID_MMFR2 is shown in Figure 2-118 and described in Table 2-144.
Memory Model Feature 2 General information on the memory model and memory management support.
Figure 2-118. ID_MMFR2 Register
31 30 29 28 27 26 25 24
RESERVED WAIT_FOR_IN
TERRUPT_ST
ALLING
R-X R-1h
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED
R-X
Table 2-144. ID_MMFR2 Register Field Descriptions
Bit Field Type Reset Description
31-25 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
24 WAIT_FOR_INTERRUPT R 1h
wait for interrupt stalling 0x0: Not supported 0x1: Wait for interrupt
_STALLING
supported
23-0 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
191
SWCU117AFebruary 2015Revised March 2015
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