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Cortex-M3 Processor Registers

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2.7.4.43 ID_PFR1 Register (Offset = D44h) [reset = X]

ID_PFR1 is shown in Figure 2-113 and described in Table 2-139.

Processor Feature 1

Figure 2-113. ID_PFR1 Register

31 30 29 28 27 26 25 24

RESERVED

R-X

23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8

RESERVED MICROCONTROLLER_PROGRAMMERS_MODEL

R-X R-2h

7 6 5 4 3 2 1 0

RESERVED

R-X

Table 2-139. ID_PFR1 Register Field Descriptions

Bit Field Type Reset Description

31-12 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

11-8 MICROCONTROLLER_P R 2h

Microcontroller programmer's model 0x0: Not supported 0x2: Two-

ROGRAMMERS_MODEL

stack support

7-0 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

186

SWCU117A–February 2015–Revised March 2015

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