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Cortex-M3 Processor Registers

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2.7.4.41 AFSR Register (Offset = D3Ch) [reset = X]

AFSR is shown in Figure 2-111 and described in Table 2-137.

Auxiliary Fault Status This register is used to determine additional system fault information to software.

Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one

to the corresponding bit. Auxiliary fault inputs to the CPU are tied to 0.

Figure 2-111. AFSR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IMPDEF

R/W-X

Table 2-137. AFSR Register Field Descriptions

Bit Field Type Reset Description

31-0 IMPDEF R/W X

Implementation defined. The bits map directly onto the signal

assignment to the auxiliary fault inputs. Tied to 0

184

SWCU117A–February 2015–Revised March 2015

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