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Cortex-M3 Processor Registers

2.7.4.40 BFAR Register (Offset = D38h) [reset = 0h]

BFAR is shown in Figure 2-110 and described in Table 2-136.

Bus Fault Address This register is used to read the address of the location that generated a Bus Fault.

Figure 2-110. BFAR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRESS

R/W-0h

Table 2-136. BFAR Register Field Descriptions

Bit Field Type Reset Description

31-0 ADDRESS R/W 0h

Bus fault address field. This field is the data address of a faulted

load or store attempt. When an unaligned access faults, the address

is the address requested by the instruction, even if that is not the

address that faulted. Flags CFSR.IBUSERR, CFSR.PRECISERR,

CFSR.IMPRECISERR, CFSR.UNSTKERR and CFSR.STKERR in

combination with CFSR.BFARVALID indicate the cause of the fault.

183

SWCU117A–February 2015–Revised March 2015

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