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Cortex-M3 Processor Registers

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2.7.4.39 MMFAR Register (Offset = D34h) [reset = 0h]

MMFAR is shown in Figure 2-109 and described in Table 2-135.

Mem Manage Fault Address This register is used to read the address of the location that caused a

Memory Manage Fault.

Figure 2-109. MMFAR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRESS

R/W-0h

Table 2-135. MMFAR Register Field Descriptions

Bit Field Type Reset Description

31-0 ADDRESS R/W 0h

Mem Manage fault address field. This field is the data address of a

faulted load or store attempt. When an unaligned access faults, the

address is the actual address that faulted. Because an access can

be split into multiple parts, each aligned, this address can be any

offset in the range of the requested size. Flags CFSR.IACCVIOL,

CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in

combination with CFSR.MMARVALIDindicate the cause of the fault.

182

SWCU117A–February 2015–Revised March 2015

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