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www.ti.com Cortex-M3 Processor Registers
2.7.4.38 DFSR Register (Offset = D30h) [reset = X]
DFSR is shown in Figure 2-108 and described in Table 2-134.
Debug Fault Status This register is used to monitor external debug requests, vector catches, data
watchpoint match, BKPT instruction execution, halt requests. Multiple flags in the Debug Fault Status
Register can be set when multiple fault conditions occur. The register is read/write clear. This means that
it can be read normally. Writing a 1 to a bit clears that bit. Note that these bits are not set unless the event
is caught. This means that it causes a stop of some sort. If halting debug is enabled, these events stop
the processor into debug. If debug is disabled and the debug monitor is enabled, then this becomes a
debug monitor handler call, if priority permits. If debug and the monitor are both disabled, some of these
events are Hard Faults, and some are ignored.
Figure 2-108. DFSR Register
31 30 29 28 27 26 25 24
RESERVED
R/W-X
23 22 21 20 19 18 17 16
RESERVED
R/W-X
15 14 13 12 11 10 9 8
RESERVED
R/W-X
7 6 5 4 3 2 1 0
RESERVED EXTERNAL VCATCH DWTTRAP BKPT HALTED
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
Table 2-134. DFSR Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
4 EXTERNAL R/W X
External debug request flag. The processor stops on next instruction
boundary. 0x0: External debug request signal not asserted 0x1:
External debug request signal asserted
3 VCATCH R/W X
Vector catch flag. When this flag is set, a flag in one of the local fault
status registers is also set to indicate the type of fault. 0x0: No vector
catch occurred 0x1: Vector catch occurred
2 DWTTRAP R/W X
Data Watchpoint and Trace (DWT) flag. The processor stops at the
current instruction or at the next instruction. 0x0: No DWT match
0x1: DWT match
1 BKPT R/W X
BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch
code, and also by normal code. Return PC points to breakpoint
containing instruction. 0x0: No BKPT instruction execution 0x1:
BKPT instruction execution
0 HALTED R/W X
Halt request flag. The processor is halted on the next instruction.
0x0: No halt request 0x1: Halt requested by NVIC, including step
181
SWCU117A–February 2015–Revised March 2015
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