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2.7.4.36 CFSR Register (Offset = D28h) [reset = X]
CFSR is shown in Figure 2-106 and described in Table 2-132.
Configurable Fault Status This register is used to obtain information about local faults. These registers
include three subsections: The first byte is Memory Manage Fault Status Register (MMFSR). The second
byte is Bus Fault Status Register (BFSR). The higher half-word is Usage Fault Status Register (UFSR).
The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one
fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a
1 to any bit clears that bit. The CFSR is byte accessible. CFSR or its subregisters can be accessed as
follows: The following accesses are possible to the CFSR register: - access the complete register with a
word access to 0xE000ED28. - access the MMFSR with a byte access to 0xE000ED28 - access the
MMFSR and BFSR with a halfword access to 0xE000ED28 - access the BFSR with a byte access to
0xE000ED29 - access the UFSR with a halfword access to 0xE000ED2A.
Figure 2-106. CFSR Register
31 30 29 28 27 26 25 24
RESERVED DIVBYZERO UNALIGNED
R/W-X R/W-X R/W-X
23 22 21 20 19 18 17 16
RESERVED NOCP INVPC INVSTATE UNDEFINSTR
R/W-X R/W-X R/W-X R/W-X R/W-X
15 14 13 12 11 10 9 8
BFARVALID RESERVED STKERR UNSTKERR IMPRECISERR PRECISERR IBUSERR
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
7 6 5 4 3 2 1 0
MMARVALID RESERVED MSTKERR MUNSTKERR RESERVED DACCVIOL IACCVIOL
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
Table 2-132. CFSR Register Field Descriptions
Bit Field Type Reset Description
31-26 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
25 DIVBYZERO R/W X
When CCR.DIV_0_TRP (see Configuration Control Register on page
8-26) is enabled and an SDIV or UDIV instruction is used with a
divisor of 0, this fault occurs The instruction is executed and the
return PC points to it. If CCR.DIV_0_TRP is not set, then the divide
returns a quotient of 0.
24 UNALIGNED R/W X
When CCR.UNALIGN_TRP is enabled, and there is an attempt to
make an unaligned memory access, then this fault occurs. Unaligned
LDM/STM/LDRD/STRD instructions always fault irrespective of the
setting of CCR.UNALIGN_TRP.
23-20 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
19 NOCP R/W X
Attempt to use a coprocessor instruction. The processor does not
support coprocessor instructions.
18 INVPC R/W X
Attempt to load EXC_RETURN into PC illegally. Invalid instruction,
invalid context, invalid value. The return PC points to the instruction
that tried to set the PC.
17 INVSTATE R/W X
Indicates an attempt to execute in an invalid EPSR state (e.g. after a
BX type instruction has changed state). This includes state change
after entry to or return from exception, as well as from inter-working
instructions. Return PC points to faulting instruction, with the invalid
state.
16 UNDEFINSTR R/W X
This bit is set when the processor attempts to execute an undefined
instruction. This is an instruction that the processor cannot decode.
The return PC points to the undefined instruction.
178
SWCU117A–February 2015–Revised March 2015
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