User manual

www.ti.com Cortex-M3 Processor Registers
Table 2-131. SHCSR Register Field Descriptions (continued)
Bit Field Type Reset Description
10 PENDSVACT R X
PendSV active 0x0: Not active 0x1: Active
9 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
8 MONITORACT R X
Debug monitor active
0h = Exception is not active
1h = Exception is active
7 SVCALLACT R X
SVCall active
0h = Exception is not active
1h = Exception is active
6-4 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
3 USGFAULTACT R X
UsageFault exception active
0h = Exception is not active
1h = Exception is active
2 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1 BUSFAULTACT R X
BusFault exception active
0h = Exception is not active
1h = Exception is active
0 MEMFAULTACT R X
MemManage exception active
0h = Exception is not active
1h = Exception is active
177
SWCU117A–February 2015–Revised March 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated