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Cortex-M3 Processor Registers

2.7.4.34 SHPR3 Register (Offset = D20h) [reset = X]

SHPR3 is shown in Figure 2-104 and described in Table 2-130.

System Handlers 12-15 Priority This register is used to prioritize the following system handlers: SysTick,

PendSV and Debug Monitor. System Handlers are a special class of exception handler that can have their

priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled,

the fault is always treated as a Hard Fault.

Figure 2-104. SHPR3 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PRI_15 PRI_14 RESERVED PRI_12

R/W-X R/W-X R/W-X R/W-X

Table 2-130. SHPR3 Register Field Descriptions

Bit Field Type Reset Description

31-24 PRI_15 R/W X

Priority of system handler 15. SysTick exception

23-16 PRI_14 R/W X

Priority of system handler 14. Pend SV

15-8 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

7-0 PRI_12 R/W X

Priority of system handler 12. Debug Monitor

175

SWCU117A–February 2015–Revised March 2015

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