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Cortex-M3 Processor Registers

2.7.4.32 SHPR1 Register (Offset = D18h) [reset = X]

SHPR1 is shown in Figure 2-102 and described in Table 2-128.

System Handlers 4-7 Priority This register is used to prioritize the following system handlers: Memory

manage, Bus fault, and Usage fault. System Handlers are a special class of exception handler that can

have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled).

When disabled, the fault is always treated as a Hard Fault.

Figure 2-102. SHPR1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PRI_6 PRI_5 PRI_4

R/W-X R/W-X R/W-X R/W-X

Table 2-128. SHPR1 Register Field Descriptions

Bit Field Type Reset Description

31-24 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

23-16 PRI_6 R/W X

Priority of system handler 6. UsageFault

15-8 PRI_5 R/W X

Priority of system handler 5: BusFault

7-0 PRI_4 R/W X

Priority of system handler 4: MemManage

173

SWCU117A–February 2015–Revised March 2015

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