User manual

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Functional Overview

In addition, the CC26xx microcontroller offers the advantages of ARM's widely available development

tools, SoC infrastructure IP applications, and a large user community. Additionally, the microcontroller

uses ARMThumb

-compatible Thumb

-2 instruction set to reduce memory requirements and, thereby,

cost.

TI offers a complete solution to get to market quickly, with evaluation and development boards, white

papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and

distributor network.

1.3 Functional Overview

The following sections provide an overview of the features of the CC26xx microcontroller.

1.3.1 ARM Cortex-M3

The following sections provide an overview of the ARM Cortex-M3 processor core and instruction set, the

integrated system timer (SysTick), and the NVIC.

1.3.1.1 Processor Core

The CC26xx is designed around an ARM Cortex-M3 processor core. The ARM Cortex-M3 processor

provides the core for a high-performance, low-cost platform that meets the needs of minimal memory

implementation, reduced pin count, and low power consumption, while delivering outstanding

computational performance and exceptional system response to interrupts.

• 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications

• Outstanding processing performance combined with fast interrupt handling

• Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM

core in a compact memory size, usually associated with 8- and 16-bit devices, typically in the range of

a few kilobytes of memory for microcontroller-class applications

– Single-cycle multiply instruction and hardware divide

– Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral

control

– Unaligned data access, enabling efficient packing of data into memory

• Fast code execution permits slower processor clock or increases sleep mode time

• Harvard architecture characterized by separate buses for instruction and data

• Efficient processor core, system, and memories

• Hardware division and fast multiplier

• Deterministic, high-performance interrupt handling for time-critical applications

• Enhanced system debug with extensive breakpoint capabilities and debugging through power modes

• Compact JTAG interface reduces the number of pins required for debugging

• Ultra-low power consumption with integrated sleep modes

• Up to 48-MHz operation

SWCU117A–February 2015–Revised March 2015 Architectural Overview

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