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Cortex-M3 Processor Registers

2.7.4.25 NVIC_IPR8 Register (Offset = 420h) [reset = X]

NVIC_IPR8 is shown in Figure 2-95 and described in Table 2-121.

Irq 32 to 35 Priority This register is used to assign a priority from 0 to 255 to each of the available

interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority

Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 2-95. NVIC_IPR8 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PRI_33 PRI_32

R/W-X R/W-X R/W-X

Table 2-121. NVIC_IPR8 Register Field Descriptions

Bit Field Type Reset Description

31-16 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

15-8 PRI_33 R/W X

Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details).

7-0 PRI_32 R/W X

Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details).

165

SWCU117A–February 2015–Revised March 2015

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