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Cortex-M3 Processor Registers

2.7.4.23 NVIC_IPR6 Register (Offset = 418h) [reset = X]

NVIC_IPR6 is shown in Figure 2-93 and described in Table 2-119.

Irq 24 to 27 Priority This register is used to assign a priority from 0 to 255 to each of the available

interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority

Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 2-93. NVIC_IPR6 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PRI_27 PRI_26 PRI_25 PRI_24

R/W-X R/W-X R/W-X R/W-X

Table 2-119. NVIC_IPR6 Register Field Descriptions

Bit Field Type Reset Description

31-24 PRI_27 R/W X

Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details).

23-16 PRI_26 R/W X

Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details).

15-8 PRI_25 R/W X

Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details).

7-0 PRI_24 R/W X

Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details).

163

SWCU117A–February 2015–Revised March 2015

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