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Cortex-M3 Processor Registers

2.7.4.21 NVIC_IPR4 Register (Offset = 410h) [reset = X]

NVIC_IPR4 is shown in Figure 2-91 and described in Table 2-117.

Irq 16 to 19 Priority This register is used to assign a priority from 0 to 255 to each of the available

interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority

Registers changes based on the setting in AIRCR.PRIGROUP.

Figure 2-91. NVIC_IPR4 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PRI_19 PRI_18 PRI_17 PRI_16

R/W-X R/W-X R/W-X R/W-X

Table 2-117. NVIC_IPR4 Register Field Descriptions

Bit Field Type Reset Description

31-24 PRI_19 R/W X

Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details).

23-16 PRI_18 R/W X

Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details).

15-8 PRI_17 R/W X

Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details).

7-0 PRI_16 R/W X

Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details).

161

SWCU117A–February 2015–Revised March 2015

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