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2.7.4.15 NVIC_IABR0 Register (Offset = 300h) [reset = X]
NVIC_IABR0 is shown in Figure 2-85 and described in Table 2-111.
Irq 0 to 31 Active Bit This register is used to determine which interrupts are active. Each flag in the
register corresponds to one interrupt.
Figure 2-85. NVIC_IABR0 Register
31 30 29 28 27 26 25 24
ACTIVE31 ACTIVE30 ACTIVE29 ACTIVE28 ACTIVE27 ACTIVE26 ACTIVE25 ACTIVE24
R-X R-X R-X R-X R-X R-X R-X R-X
23 22 21 20 19 18 17 16
ACTIVE23 ACTIVE22 ACTIVE21 ACTIVE20 ACTIVE19 ACTIVE18 ACTIVE17 ACTIVE16
R-X R-X R-X R-X R-X R-X R-X R-X
15 14 13 12 11 10 9 8
ACTIVE15 ACTIVE14 ACTIVE13 ACTIVE12 ACTIVE11 ACTIVE10 ACTIVE9 ACTIVE8
R-X R-X R-X R-X R-X R-X R-X R-X
7 6 5 4 3 2 1 0
ACTIVE7 ACTIVE6 ACTIVE5 ACTIVE4 ACTIVE3 ACTIVE2 ACTIVE1 ACTIVE0
R-X R-X R-X R-X R-X R-X R-X R-X
Table 2-111. NVIC_IABR0 Register Field Descriptions
Bit Field Type Reset Description
31 ACTIVE31 R X
Reading 0 from this bit implies that interrupt line 31 is not active.
Reading 1 from this bit implies that the interrupt line 31 is active (See
EVENT:CPUIRQSEL31.EV for details).
30 ACTIVE30 R X
Reading 0 from this bit implies that interrupt line 30 is not active.
Reading 1 from this bit implies that the interrupt line 30 is active (See
EVENT:CPUIRQSEL30.EV for details).
29 ACTIVE29 R X
Reading 0 from this bit implies that interrupt line 29 is not active.
Reading 1 from this bit implies that the interrupt line 29 is active (See
EVENT:CPUIRQSEL29.EV for details).
28 ACTIVE28 R X
Reading 0 from this bit implies that interrupt line 28 is not active.
Reading 1 from this bit implies that the interrupt line 28 is active (See
EVENT:CPUIRQSEL28.EV for details).
27 ACTIVE27 R X
Reading 0 from this bit implies that interrupt line 27 is not active.
Reading 1 from this bit implies that the interrupt line 27 is active (See
EVENT:CPUIRQSEL27.EV for details).
26 ACTIVE26 R X
Reading 0 from this bit implies that interrupt line 26 is not active.
Reading 1 from this bit implies that the interrupt line 26 is active (See
EVENT:CPUIRQSEL26.EV for details).
25 ACTIVE25 R X
Reading 0 from this bit implies that interrupt line 25 is not active.
Reading 1 from this bit implies that the interrupt line 25 is active (See
EVENT:CPUIRQSEL25.EV for details).
24 ACTIVE24 R X
Reading 0 from this bit implies that interrupt line 24 is not active.
Reading 1 from this bit implies that the interrupt line 24 is active (See
EVENT:CPUIRQSEL24.EV for details).
23 ACTIVE23 R X
Reading 0 from this bit implies that interrupt line 23 is not active.
Reading 1 from this bit implies that the interrupt line 23 is active (See
EVENT:CPUIRQSEL23.EV for details).
22 ACTIVE22 R X
Reading 0 from this bit implies that interrupt line 22 is not active.
Reading 1 from this bit implies that the interrupt line 22 is active (See
EVENT:CPUIRQSEL22.EV for details).
21 ACTIVE21 R X
Reading 0 from this bit implies that interrupt line 21 is not active.
Reading 1 from this bit implies that the interrupt line 21 is active (See
EVENT:CPUIRQSEL21.EV for details).
153
SWCU117A–February 2015–Revised March 2015
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