User manual

Cortex-M3 Processor Registers

www.ti.com

2.7.4.14 NVIC_ICPR1 Register (Offset = 284h) [reset = X]

NVIC_ICPR1 is shown in Figure 2-84 and described in Table 2-110.

Irq 32 to 63 Clear Pending This register is used to clear pending interrupts and determine which interrupts

are currently pending.

Figure 2-84. NVIC_ICPR1 Register

31 30 29 28 27 26 25 24

RESERVED

R/W-X

23 22 21 20 19 18 17 16

RESERVED

R/W-X

15 14 13 12 11 10 9 8

RESERVED

R/W-X

7 6 5 4 3 2 1 0

RESERVED CLRPEND33 CLRPEND32

R/W-X R/W-X R/W-X

Table 2-110. NVIC_ICPR1 Register Field Descriptions

Bit Field Type Reset Description

31-2 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1 CLRPEND33 R/W X

Writing 0 to this bit has no effect, writing 1 to this bit clears the

corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV

for details). Reading the bit returns its current state.

0 CLRPEND32 R/W X

Writing 0 to this bit has no effect, writing 1 to this bit clears the

corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV

for details). Reading the bit returns its current state.

152

SWCU117A–February 2015–Revised March 2015

Submit Documentation Feedback