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Cortex-M3 Processor Registers www.ti.com
Table 2-109. NVIC_ICPR0 Register Field Descriptions (continued)
Bit Field Type Reset Description
20 CLRPEND20 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV
for details). Reading the bit returns its current state.
19 CLRPEND19 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV
for details). Reading the bit returns its current state.
18 CLRPEND18 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV
for details). Reading the bit returns its current state.
17 CLRPEND17 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV
for details). Reading the bit returns its current state.
16 CLRPEND16 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV
for details). Reading the bit returns its current state.
15 CLRPEND15 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV
for details). Reading the bit returns its current state.
14 CLRPEND14 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV
for details). Reading the bit returns its current state.
13 CLRPEND13 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV
for details). Reading the bit returns its current state.
12 CLRPEND12 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV
for details). Reading the bit returns its current state.
11 CLRPEND11 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV
for details). Reading the bit returns its current state.
10 CLRPEND10 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV
for details). Reading the bit returns its current state.
9 CLRPEND9 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV
for details). Reading the bit returns its current state.
8 CLRPEND8 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV
for details). Reading the bit returns its current state.
7 CLRPEND7 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV
for details). Reading the bit returns its current state.
6 CLRPEND6 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV
for details). Reading the bit returns its current state.
5 CLRPEND5 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV
for details). Reading the bit returns its current state.
4 CLRPEND4 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV
for details). Reading the bit returns its current state.
3 CLRPEND3 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV
for details). Reading the bit returns its current state.
150
SWCU117A–February 2015–Revised March 2015
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