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1471

RF Core HAL

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Table 23-19. Format of an MCE/RFE Override Mode Entry

Bit Index Bit Field Name Description

0–1 entryType 11: Firmware defined parameter

2–3 entrySubType 01: MCE/RFE override mode

4–7 Reserved

0: Run MCE from ROM

8 bMceUseRam

1: Run MCE from RAM

9–11 mceRomBank MCE ROM bank to run from

0: Run RFE from ROM

12 bRfeUseRam

1: Run RFE from RAM

13–15 rfeRomBank RFE ROM bank to run from

16–23 mceMode Mode to send to MCE

24–31 rfeMode Mode to send to RFE

Table 23-20. Format of a Center Frequency Entry

Bit Index Bit Field Name Description

0–1 entryType 11: Firmware defined parameter

2–3 entrySubType 10: Special configuration

4–7 specialType 0001: Center frequency entry

8 Reserved

9 bAutoTxIf If 1, set TX IF to RX IF

10 bApplyRx If 1, use invRfFreq to recalculate RX IF

11 bApplyTx If 1, use invRfFreq to recalculate TX shape

Value where fRFMHz is center frequency in MHz:

12–31 invRfFreq

(12 × 24 × 220) / (fRFMHz × loDivider)

Table 23-21. Format of an End of List Entry

Bit Index Bit Field Name Description

0–1 entryType 11: Firmware defined parameter

2–3 entrySubType 11: End of list segment

0x0: End of list

0x1: SRAM. Base = 0x20000000

0x2: RF core RAM. Base = 0x21000000

0x3: Flash. Base = 0xA0000000

0x4: RF core ROM. Base = 0x00000000

(1)

4–7 nextEntryRegion 0x5: BROM. Base = 0x100000002

0x6. GPRAM. Base = 0x110000002

0x7: Registers. Base = 0x400000002

0x8: FCFG. Base = 0x500000002

0xF: End of list

Others: Reserved

Address offset for next list part. Next address is:

8–31 addrOffset

Base + (addrOffset × 4)

(1)

Not recommended. Included for completeness; will only work if pointer range checks have been

disabled.

1472

Radio SWCU117A–February 2015–Revised March 2015

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