User manual

www.ti.com I2S Registers
22.10.1.30 IRQCLR Register (Offset = 7Ch) [reset = X]
IRQCLR is shown in Figure 22-37 and described in Table 22-31.
Interrupt Clear Register
Figure 22-37. IRQCLR Register
31 30 29 28 27 26 25 24
RESERVED
W-X
23 22 21 20 19 18 17 16
RESERVED
W-X
15 14 13 12 11 10 9 8
RESERVED
W-X
7 6 5 4 3 2 1 0
RESERVED AIF_DMA_IN AIF_DMA_OUT WCLK_TIMEO BUS_ERR WCLK_ERR PTR_ERR
UT
W-X W-X W-X W-X W-X W-X W-X
Table 22-31. IRQCLR Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
5 AIF_DMA_IN W X
1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set
criteria was given at the same time in which the clear will be ignored)
4 AIF_DMA_OUT W X
1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set
criteria was given at the same time in which the clear will be ignored)
3 WCLK_TIMEOUT W X
1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set
criteria was given at the same time in which the clear will be ignored)
2 BUS_ERR W X
1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria
was given at the same time in which the clear will be ignored)
1 WCLK_ERR W X
1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set
criteria was given at the same time in which the clear will be ignored)
0 PTR_ERR W X
1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria
was given at the same time in which the clear will be ignored)
1453
SWCU117A–February 2015–Revised March 2015 Integrated Interchip Sound (I2S) Module
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated