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I2S Registers

22.10.1.26 STMPWCNTCAPT1 Register (Offset = 68h) [reset = X]

STMPWCNTCAPT1 is shown in Figure 22-33 and described in Table 22-27.

Captured WCLK Counter Value, Capture Channel 1

Figure 22-33. STMPWCNTCAPT1 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CAPT_VALUE

R-X R-X

Table 22-27. STMPWCNTCAPT1 Register Field Descriptions

Bit Field Type Reset Description

31-16 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

15-0 CAPT_VALUE R X

Channel 1 is idle and can not be sampled from an external event as

with Channel 0 STMPWCNTCAPT0

1449

SWCU117A–February 2015–Revised March 2015 Integrated Interchip Sound (I2S) Module

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