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I2S Registers

22.10.1.20 STMPWSET Register (Offset = 50h) [reset = X]

STMPWSET is shown in Figure 22-27 and described in Table 22-21.

WCLK Counter Set Operation

Figure 22-27. STMPWSET Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED VALUE

R-X R/W-X

Table 22-21. STMPWSET Register Field Descriptions

Bit Field Type Reset Description

31-16 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

15-0 VALUE R/W X

WCLK counter modification: Sets the running WCLK counter equal

to the written value.

1443

SWCU117A–February 2015–Revised March 2015 Integrated Interchip Sound (I2S) Module

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