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Cortex-M3 Processor Registers

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2.7.4.10 NVIC_ICER1 Register (Offset = 184h) [reset = X]

NVIC_ICER1 is shown in Figure 2-80 and described in Table 2-106.

Irq 32 to 63 Clear Enable This register is used to disable interrupts and determine which interrupts are

currently enabled.

Figure 2-80. NVIC_ICER1 Register

31 30 29 28 27 26 25 24

RESERVED

R/W-X

23 22 21 20 19 18 17 16

RESERVED

R/W-X

15 14 13 12 11 10 9 8

RESERVED

R/W-X

7 6 5 4 3 2 1 0

RESERVED CLRENA33 CLRENA32

R/W-X R/W-X R/W-X

Table 2-106. NVIC_ICER1 Register Field Descriptions

Bit Field Type Reset Description

31-2 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1 CLRENA33 R/W X

Writing 0 to this bit has no effect, writing 1 to this bit disables the

interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details).

Reading the bit returns its current enable state.

0 CLRENA32 R/W X

Writing 0 to this bit has no effect, writing 1 to this bit disables the

interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details).

Reading the bit returns its current enable state.

144

SWCU117A–February 2015–Revised March 2015

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